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| 256 x 8-Bit Static CMOS RAM NMOS-Compatible Preliminary DataCMOS IC PFeatures q q q SAE 81C52 q q q q q 256 x 8-bit organization Standby mode Compatible with the NMOS and CMOS versions of the microprocessor/microcontroller families SAB 8086, SAB 8051 Very low power dissipation Data retention up to VDD 1 V Three different chip select inputs for two chip select modes No increasing power consumption in standby mode if the control inputs are on undefined potential Temperature range - 40 to 110 C P-DIP-16-1 P-DSO-20-1 Type SAE 81C52 P SAE 81C52 G Ordering Code Q67100-H9017 Q67100-H9015 Package P-DIP-16-1 P-DSO-20-1 (SMD) The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051. All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 ... AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR. The power consumption is max. 5.5 W in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential. Semiconductor Group 1 09.94 SAE 81C52 Pin Configurations (top view) SAE 81C52 P SAE 81C52 G Semiconductor Group 2 SAE 81C52 Pin Definitions and Functions SAE 81C52 G Pin No. 1, 2, 4, 5, 6 7, 12, 14 15 SAE 81C52 P Pin No. 1...6 10, 11 12 AD0 ... 7 CS1 Address/data lines Chip select 1 (standby) active low; inhibits all lines including control lines Address latch enable Write enable Read enable Power supply GND (0 V) Chip select 2; inhibits control inputs RD, WR Counterpart to CS2 Symbol Function 16 17 19 20 9 10 11 13 14 15 16 7 8 9 ALE WR RD VDD VSS CS2 CS3 Semiconductor Group 3 SAE 81C52 Block Diagram Semiconductor Group 4 SAE 81C52 Logic Symbol Truth Table CS1 L H H H H H CS2 * X H H L X CS3 * X L L X H ALE * H L L L L RD * H L H X X WR * H H L X X AD0 ... AD7 Floating (tristate) Addresses to memory Data from memory Data to memory Floating (tristate) Floating (tristate) Function Standby Store addresses Read Write None None *: Level = VSS ... VDD X: Level = low or high Semiconductor Group 5 SAE 81C52 Absolute Maximum Ratings TA = - 40 to 110 C Parameter Supply voltage referred to GND (VSS) All input and output voltages Total power dissipation Power dissipation for each output Junction temperature Storage temperature Thermal resistance system - air P-DIP-16-1 P-DSO-20-1 Symbol Limit Values 0 to 6 VSS - 0.3 VDD + 0.3 250 50 125 - 55 to 125 70 95 Unit V V V mW mW C C K/W K/W VDD VIM Ptot PQ Tj Tstg Rth SA Rth SA Operating Range Supply voltage Ambient temperature VDD TA 4.5 to 5.5 - 40 to 110 V C Semiconductor Group 6 SAE 81C52 DC Characteristics TA = - 40 to 110 C; VDD = 4.25 V to 5.5 V; VSS = 0 V Parameter Symbol Limit Values min. Standby supply current Supply current Standby voltage for data retention L-input current (for each input) Output leakage current L-input voltage H-input voltage L-output voltage H-output voltage L-input voltage CS1 H-input voltage CS1 max. 1 3 1.0 1 1 A mA V A A V V V V V V Unit Test Condition IDD IDD VDD IIL IQLK VIL VIH VQL VQH VIL VIH VSS 2.2 2.6 VDD = 5.5 V; TA = 25 C; VCS1 = 0 V tcyc = 1 s; VDD = 5.5 V; CL = 100 pF VI = 0 to VDD VQ = 0 to VDD tristate 0.8 VDD 0.4 IQL = 1 mA IQL = 1 mA VSS VDD - 1 1 VDD Semiconductor Group 7 SAE 81C52 AC Characteristics TA = - 40 to 110 C; VDD = 4.5 to 5.5 V; VSS = 0 V Parameter Symbol Limit Values min. ALE pulse width ALE low before RD low RD high before ALE high ALE low before WR low WR high before ALE high Address setup before ALE Address hold after ALE WR or RD pulse width Data setup before WR Data hold after WR Data hold after RD Chip select (2, 3) before RD, WR Chip select (2, 3) after RD, WR Chip select 1 before ALE Chip select 1 after RD, WR Output delay time Input capacitance to VSS (for each input) max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200 10 ns pF Unit tLHLL tLLRL tRHLH tLLWL tWHLH tAVLL tLLAX tWLWH tQVWH tWHQX tRHDX tCS tSC tCSLH tCSWH tRLDV CI 100 50 18 50 18 18 30 250 50 18 90 50 18 20 50 Semiconductor Group 8 SAE 81C52 Timing Diagram Semiconductor Group 9 SAE 81C52 Application Circuit SAE 81C52 with the C SAB 8051 Semiconductor Group 10 |
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